SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

World Intellectual Property Organization Patent

APP PUB NO WO-2010001506-A1
SERIAL NO

PCTJP2009000799

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Abstract

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Disclosed is a layout structure for semiconductor integrated circuit devices, which can prevent thinning or disconnection of a metal wiring near a cell boundary without accompanying an increase in the data amount or processing time for OPC. A first cell and a second cell, each having a transistor and an internal wiring for performing a circuit function, are arranged adjacent to each other in a first direction in a region lying between a source wiring (m1) and a ground wiring (m2) which are so arranged as to extend in the first direction. In the boundary portion between the first cell and the second cell, a metal wiring (d2) extending in a second direction, which is perpendicular to the first direction, is arranged so that the metal wiring (d2) is not short-circuited with the source wiring (m1) and the ground wiring (m2).

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Patent Owner(s)

Patent OwnerAddress
PANASONIC CORPORATIONJP1006 OAZA KADOMA KADOMA-SHI OSAKA 571-8501

International Classification(s)

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Inventor(s)

Inventor Name Address
NISHIMURA HIDETOSHI -
TANIGUCHI HIROKI 406-3 TSUICHIBA ABOSHI-KU HIMEJI-SHI HYOGO
SHIMBO HIROYUKI -
TOUBOU TETSUROU -
YONEDA HISAKO -

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