Emulation system having multiple emulator clock cycles per emulated clock cycle
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United States of America Patent
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Jul 6, 1999
Issued Date -
N/A
app pub date -
Nov 12, 1996
filing date -
May 13, 1994
priority date (Note) -
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Abstract
An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit. The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.
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