Method for remapping logic modules to resources of a programmable gate array
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United States of America Patent
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Jun 18, 2002
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N/A
app pub date -
Jan 19, 1999
filing date -
Mar 27, 1998
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Abstract
A method is provided for remapping logic modules to resources of a programmable gate array. Connections are specified between at least two logic modules, wherein each module has a respective floorplan that includes a set of circuit elements. A first set of resources of the programmable gate array is compared to a second set of resources, wherein the second set of resources are those resources required by the sets of circuit elements. If the first set of resources covers the second set of resources, the floorplans of the logic modules are combined into a single floorplan that maps to the first set of resources.
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