DYNAMIC SCALING OF MEMORY AND BUS FREQUENCIES
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United States of America Patent
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Issued Date -
Apr 16, 2015
app pub date -
Feb 10, 2014
filing date -
Oct 11, 2013
priority date (Note) -
Abandoned
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Abstract
Systems and methods for controlling a frequency of system memory and/or system bus on a computing device are disclosed. The method may include monitoring a number of read/write events occurring in connection with a hardware device during a length of time with a performance counter and calculating an effective data transfer rate based upon the amount of data transferred. The method also includes periodically adjusting a frequency of at least one of the system memory and the system bus based upon the effective data transfer rate and dynamically tuning a threshold number of events that trigger an interrupt based upon a history of the number of read/write events. In addition, the method includes receiving the interrupt from the performance counter when the threshold number of read/write events occurs and adjusting the frequency of at least one of the system memory and the system bus when the interrupt occurs.
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