CACHE CONTROL APPARATUS AND METHOD
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United States of America Patent
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Issued Date -
May 21, 2015
app pub date -
Apr 15, 2014
filing date -
Nov 20, 2013
priority date (Note) -
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Abstract
Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.
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