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Abstract

A method of forming a conductive via plug or an interconnect line, or both, of solid ductile metal within an integrated circuit using plastic deformation of the solid metal, and a dry polishing method of removing excess metal from a metal layer atop an underlying layer on a semiconductor substrate wafer. The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. If both conductive via plugs and interconnect lines are both required within the circuit, a first masking step defines the interconnect lines. A first etch creates channels in the interconnect line locations. A second masking step defines the vias. A second etch creates the vias which pass through the dielectric layer to conductive regions below where contact is to be made. A layer of solid ductile metal is then deposited on top of the dielectric layer. Using a disk or pad which is held in contact with the ductile metal layer, metal of the ductile layer is mechanically worked to plastically deformed more deeply into the channels and vias. The wafer is then dry polished with a solid material having a hardness which is less than both the hardness of the metal and the hardness of the underlying layer to provide remaining metal from the metal layer which is only in conductive interconnect lines or vias.

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First Claim