Manufacturing method and apparatus of a semiconductor integrated circuit device
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United States of America Patent
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Apr 8, 1997
Grant Date -
N/A
app pub date -
Sep 22, 1993
filing date -
Sep 22, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
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