Sets and holds in virtual time logic simulation for parallel processors
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United States of America Patent
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Jul 15, 1997
Grant Date -
N/A
app pub date -
Dec 30, 1994
filing date -
Dec 30, 1994
priority date (Note) -
Expired
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Abstract
In an event-driven, virtual time logic simulation system, user-initiated requests for setting and holding simulated logic circuit elements are accommodated during forward simulation, rollback, and advance of system global virtual time.
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