Multi-chip memory apparatus and associated method

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United States of America Patent

PATENT NO 6392304
SERIAL NO

09190660

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Abstract

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A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

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Patent Owner(s)

Patent OwnerAddress
CHIP PACKAGING SOLUTIONS LLC6136 FRISCO SQUARE BLVD SUITE 385 FRISCO TX 75034

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Butler, Douglas B Colorado Springs, CO 17 312

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