Node controller for performing cache coherence control and memory-shared multiprocessor system
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United States of America Patent
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Sep 7, 2004
Grant Date -
N/A
app pub date -
Jun 2, 2000
filing date -
Jun 3, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.
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