Method and apparatus for calibration of an array of scaled electronic circuit elements
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United States of America Patent
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Jun 21, 2005
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N/A
app pub date -
Oct 24, 2002
filing date -
Jun 14, 2002
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Abstract
A method and apparatus for calibrating an electronic circuit which required scaled matching of some or all of its electronic components with nonvolatile programmably trimmable parameter sources (current, voltage, resistance, capacitance) is carried out in a top-down (highest order bit first, lowest order bit last) fashion without an analog division step. The method and apparatus are applicable, for example, to current-steering digital-to-analog converters (DACs), voltage-controlled oscillators (VCOs), voltage-steering DACs, and the like. In each of these applications the method and apparatus is used to match successive device outputs according to a desired scale factor, proceeding top-down from large output devices to smaller output devices, thereby successively shrinking the cross-device errors which accrue during the matching process.
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