Integrated circuit with timing adjustment mechanism and method
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United States of America Patent
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Sep 27, 2005
Issued Date -
N/A
app pub date -
Nov 3, 2003
filing date -
Oct 19, 1999
priority date (Note) -
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status (Latency Note)
Importance
Abstract
An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.
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