Polishing processes for shallow trench isolation substrates
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United States of America Patent
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Jun 20, 2006
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N/A
app pub date -
Oct 24, 2003
filing date -
Oct 25, 2002
priority date (Note) -
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Abstract
Methods and compositions are provided for planarizing a substrate surface with reduced or minimal topographical defect formation during a polishing process for dielectric materials. In one aspect a method is provided for polishing a substrate containing two or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, with at least one processing step using a fixed-abrasive polishing article as a polishing article. The processing steps may be used to remove all, substantially all, or a portion of the one or more dielectric layers, which may include removal of the topography, the bulk dielectric, or residual dielectric material of a dielectric layer in two or more steps.
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