Non-uniform alignment of wafer bumps with substrate solders
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United States of America Patent
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May 21, 2013
Grant Date -
Apr 21, 2011
app pub date -
May 20, 2010
filing date -
Oct 20, 2009
priority date (Note) -
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Abstract
An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.
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