Apparatus, method, and system for implementing micro page tables

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8838935
APP PUB NO 20120079232A1
SERIAL NO

12890585

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Abstract

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In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cape, Scott J Portland, US 5 306
Chappell, Robert S Portland, US 48 611
Downer, Wayne A Portland, US 11 255
Hinton, Glenn Portland, US 35 633
Moga, Adrian C Portland, US 22 343
Parthasarathy, Madhavan Portland, US 9 216
Parthasarathy, Rajesh Hillsboro, US 11 340
Ramanujan, Raj Federal Way, US 18 341
Smith, Larry O Beaverton, US 5 310
Swaminathan, Muthukumar Folsom, US 2 142
Zimmerman, David El Dorado Hills, US 24 740

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