Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
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United States of America Patent
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Nov 4, 2014
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app pub date -
Jun 26, 2009
filing date -
Jun 26, 2009
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Abstract
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
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