Reduced power mode of a cache unit

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United States of America Patent

PATENT NO 9360924
APP PUB NO 20140359330A1
SERIAL NO

13904055

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gendler, Alexander Kiriat Motzkin, IL 85 286
Novakovsky, Larisa Haifa, IL 33 138
Sabba, Ariel Karmiel, IL 10 41
Tokman, Niv Haifa, IL 4 28

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