Parallel slice processor with dynamic instruction stream mapping

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United States of America Patent

PATENT NO 9690585
APP PUB NO 20150324206A1
SERIAL NO

14300563

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Abstract

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A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eisen, Lee Evan Round Rock, US 32 566
Le, Hung Qui Austin, US 105 2671
Leenstra, Jentje Bondorf, DE 41 540
Moreira, Jose Eduardo Irvington, US 20 671
Ronchetti, Bruce Joseph Austin, US 27 635
Thompto, Brian William Austin, US 30 711
Van, Norstrand, Jr Albert James Round Rock, US 14 317

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