Method of manufacturing low CTE substrates for use with low-k flip-chip package devices

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7491624
APP PUB NO 20070087479A1
SERIAL NO

11610752

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Chien-Hsiun Hsin-Chu, TW 50 1127
Lee, Hsin-Hui Kaohsiung, TW 68 770
Lii, Mirng-Ji Hsinchu, TW 243 5682
Lu, Szu-Wei Hsinchu, TW 263 916

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation