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Abstract

A digital signal of n-bit words N.sub.i is enciphered into an enciphered signal of n-bit words R.sub.i. In an enciphering unit, a logic circuit delivers each enciphered word R.sub.i through a logic operation g performed on the word N.sub.i and on an n-bit, stored, enciphering word P.sub.i-l. An addressing circuit formulates an address word A.sub.i-l having a bits fully or partly belonging at least to the preceding enciphered word R.sub.i-l. A memory of 2.sup.a predetermined P.sub.i-l words is read by each address word A.sub.i-l to supply a corresponding word P.sub.i-l to the logic circuit for it to perform the g operation such that R.sub.i =g(N.sub.i, P.sub.i-l). A deciphering unit receives the enciphered words R.sub.i for formulating the address words A.sub.i controlling reading of the corresponding words P.sub.i out of 2.sup.a stored words. Each deciphered word N.sub.i is obtained by a logic operation h, referred to as contrary to g, performed on the enciphered word R.sub.i and on the stored word P.sub.i-l, such that N=h(R.sub.i, P.sub.i-l). The memories can be programmed by a computer, which, as per a predetermined algorithm, computes a table of words P.sub.i for a given key.

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