High selectivity etching process for metal gate N/P patterning
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United States of America Patent
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Jun 8, 2010
Issued Date -
N/A
app pub date -
Jun 5, 2009
filing date -
Jun 5, 2009
priority date (Note) -
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Abstract
A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.
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