STATIC STORES (information storage based on relative movement between record carrier and transducer G11B; semiconductor devices for storage H01L, e.g. H01L 27/108-H01L 27/115; pulse technique in general H03K, e.g. electronic switches H03K 17/00)
| Subclass | Title |
|---|---|
| 5/00 | Details of stores covered by group G11C 11/00 |
| 5/02 | Details of stores covered by group G11C 11/00 Disposition of storage elements, e.g. in the form of a matrix array |
| 5/04 | Details of stores covered by group G11C 11/00 Disposition of storage elements, e.g. in the form of a matrix array Supports for storage elements; Mounting or fixing of storage elements on such supports |
| 5/05 | Details of stores covered by group G11C 11/00 Disposition of storage elements, e.g. in the form of a matrix array Supports for storage elements; Mounting or fixing of storage elements on such supports Supporting of cores in matrix |
| 5/06 | Details of stores covered by group G11C 11/00 Arrangements for interconnecting storage elements electrically, e.g. by wiring |
| 5/08 | Details of stores covered by group G11C 11/00 Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting magnetic elements, e.g. toroidal cores |
| 5/10 | Details of stores covered by group G11C 11/00 Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors |
| 5/12 | Details of stores covered by group G11C 11/00 Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores |
| 5/14 | Details of stores covered by group G11C 11/00 Power supply arrangements (auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193; in general G05F, H02J, H02M) |
| 7/00 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) |
| 7/02 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) with means for avoiding parasitic signals |
| 7/04 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) with means for avoiding disturbances due to temperature effects |
| 7/06 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Sense amplifiers; Associated circuits (amplifiers per seH03F, H03K) |
| 7/08 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Sense amplifiers; Associated circuits (amplifiers per seH03F, H03K) Control thereof |
| 7/10 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers (level conversion circuits in general H03K 19/0175) |
| 7/12 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines |
| 7/14 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Dummy cell management; Sense reference voltage generators |
| 7/16 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Storage of analogue signals in digital stores using an arrangement comprising analogue/digital (A/D) converters, digital memories and digital/analogue (D/A) converters |
| 7/18 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Bit line organisation; Bit line lay-out |
| 7/20 | Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory |
| Publication # | Title | Filing Date | Pub Date | Patent Owner |
|---|---|---|---|---|
| 2024/0152,274 | Apparatus and Method to Provide Cache Move with Non-Volatile Mass Memory System | Oct 13, 23 | May 09, 24 | Memory Technologies LLC |
| 2024/0152,288 | Flash memory controller | Jan 15, 24 | May 09, 24 | SILICON MOTION, INC. |
| 2024/0152,294 | INTERFACE READ AFTER WRITE | Jan 11, 24 | May 09, 24 | Not available |
| 2024/0152,326 | MEMORY DEVICE AND OPERATING METHOD THEREOF | Feb 03, 23 | May 09, 24 | Taiwan Semiconductor Manufacturing Company Ltd. |
| 2024/0152,422 | FIRMWARE REPAIR FOR THREE-DIMENSIONAL NAND MEMORY | Dec 04, 23 | May 09, 24 | Not available |
| 2024/0152,435 | MEMORY DEVICE WITH FAILED MAIN BANK REPAIR USING REDUNDANT BANK | Jan 16, 24 | May 09, 24 | Not available |
| 2024/0152,469 | Self-Detecting and Data Rewriting System and Application Method Thereof | Nov 09, 22 | May 09, 24 | Not available |
| 2024/0153,420 | SHIFT REGISTER, GATE DRIVER CIRCUIT, AND DISPLAY DEVICE | Mar 30, 22 | May 09, 24 | Not available |
| 2024/0153,450 | LINE DRIVE SIGNAL ENHANCEMENT CIRCUIT, SHIFT REGISTER UNIT, DISPLAY PANEL | May 31, 21 | May 09, 24 | Not available |
| 2024/0153,462 | DISPLAY PANEL, GATE DRIVE CIRCUIT AND DRIVING METHOD THEREOF | Aug 23, 22 | May 09, 24 | Not available |
| 2024/0153,467 | DISPLAY DEVICE | Dec 19, 23 | May 09, 24 | Not available |
| 2024/0153,540 | SEMICONDUCTOR DEVICE STRUCTURE | Jan 09, 24 | May 09, 24 | Etron Technology Inc. |
| 2024/0153,541 | Integrated Assemblies and Methods Forming Integrated Assemblies | Jan 16, 24 | May 09, 24 | Micron Technology Inc. |
| 2024/0153,542 | VOLTAGE OVERSHOOT MITIGATION | Nov 04, 22 | May 09, 24 | Not available |
| 2024/0153,543 | DEVICE ID SETTING METHOD AND ELECTRONIC DEVICE APPLYING THE DEVICE ID SETTING METHOD | Jan 15, 24 | May 09, 24 | PixArt Imaging Inc. |
| 2024/0153,544 | CURRENT CONTROL CIRCUIT AND DISCHARGE ENABLE CIRCUIT FOR DISCHARGING BIT LINES OF MEMORY DEVICE AND OPERATION METHOD THEREOF | Jan 15, 24 | May 09, 24 | Not available |
| 2024/0153,545 | Systems and Methods for Controlling Power Assertion In a Memory Device | Jan 17, 24 | May 09, 24 | Not available |
| 2024/0153,546 | MEMORY DEVICE FOR PERFORMING READ PROTECTION OPERATION OF LIMITING READ OPERATION AND METHOD OF OPERATING THE SAME | Mar 30, 23 | May 09, 24 | SK HYNIX INC. |
| 2024/0153,547 | CONTROL METHOD AND SYSTEM IN 3D NAND SYSTEMS | Nov 04, 22 | May 09, 24 | Yangtze Memory Technologies Co., Ltd. |
| 2024/0153,548 | SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE | Nov 06, 23 | May 09, 24 | Not available |
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